Local Oscillator - Design

LO Design choices

The phase noise requirements for the LO are pretty strict when the frontends IMD3DR is not to be overruled by PNDR. In this section a couple of possible candidates are considered and a choice is made for the most promising approach.


Low phase noise oscillators can be built with very high-Q resonators. Crystal oscillators can easily satisfy, even rather close-in, the PM-noise requirements for this frontend. The following graph shows the single sideband noise of a simple 1 transistor low noise crystal oscillator circuit found in the ARRL handbook 2006 that I built and measured with the Crystal Notch Filter method:

Due to the nature of the notch method it is not possible to measure less than 2kHz in. The graph shows that the crystal oscillator, using an inexpensive but high-Q 14.318MHz crystal, matches the PM-noise requirements hands down, up to inside the SSB roofing filter. It would have been more correct to scale the crystal plot 1dB up for correction to 16MHz, but that does not change much!

There is so much margin left that it seems likely that also a "degraded" VXO crystal oscillator, tweaked to allow for a frequency pull of one or maybe two hundred KHz would still be sufficiently good. This would make a very effective solution if one is interested in only a portion of each amateur band, for example the CW segments. In that case we need as many VXO's as bands that we want to support. Spurs will be virtually absent, noise will be very low, but flexibility will be low also. This is a great solution for specialized receivers but not fully adequate for the general purpose amateur case.

PLL Synthesizer

Most modern commercially made amateur rig's are using a PLL based LO which is locked to a DDS reference. This approach is a compromise in an attempt to give the best of both worlds: The agile and detailed frequency resolution of the DDS combined with the low spur levels of the single loop PLL. A big challenge however is the PM-noise that inevitably comes with the VCO. Given the reciprocal mixing results shown by the better amateur equipment reviews, this type of synthesizer still has some distance to go.

To get the best out of a PLL synthesizer, sometimes a VHF or even a UHF VCO is used, allowing for high-Q cavity resonators. The output frequency is brought back into the desired frequency range with a digital divider. An interesting example of such a system is the synthesizer of the Star-10 homebrew transceiver by Cornell Drentea, KW7CD. This transceiver has been described in a 3 article series in QEX: Nov/Dec 2007, Mar/Apr 2008 and May/Jun 2008. It is an up-conversion design with the first IF at 75MHz. The synthesizer's VCO is running between 770MHz and 1050MHz and is divided down by 10. I have scaled down the PM-noise of this synthesizer to 16MHz and plotted this in the following graph. The data originates from figure 38C of the final article in QEX:

The Star-10 series is calculated from the original data, which is at 100MHz. So it is scaled down to 16MHz in order to do a comparison with the 16MHz base-line. Therefore a theoretical 15.9dB phase noise improvement (20*log(100/16)) is applied. Close-in the results are very good. From 1KHz and outwards this synthesizer is almost good enough for the 9MHz down conversion frontend, but only if that 15.9dB improvement can be realized with a practical digital divider! It is a pity however that the ultimate noise floor is already reached at 10KHz. In case of the Star-10, with its half-octave antenna BPF's, this allows a wide spectrum with potentially many strong signals to deteriorate the in-channel noise floor.

In the original Star-10 up-conversion case, this synthesizer will deliver in SSB bandwidth a PNDR of 100dB at 1KHz (PM-noise=-134dBc/Hz) and from 10KHz and outwards a PNDR of maximum 104dB (PM-noise floor=-138dBc/Hz). This shows the disadvantage of up-conversion to VHF with respect to impact of LO phase noise.

The Star-10 synthesizer PM-noise performance is very close to what is needed if it can be scaled down without additional jitter. The biggest disadvantage however is the difficulty of its practical reproducibility. Especially the utilization of a UHF VCO from Synergy Microwave makes this synthesizer probably out of reach for most of us.

The blue series in the above graph shows the performance of the ICOM IC-7700 synthesizer. The IC-7700 is modern high-end up-conversion radio with its 1st IF at 64MHz. The phase noise has been measured by Peter Hart, G3SJX, using the Reciprocal Mixing Method when receiving at 21Mhz. Therefore this series is scaled down from 85MHz to 16MHz with a factor of -14.4dB. Unlike the Star-10, it breaks through the base-line at an offset of 30KHz, but its ultimate noise floor is not known. Even when theoretically scaled down to the down-conversion scenario, the close-in performance of this synthesizer is insufficient: a decade at least. In the up-conversion scenario the PNDR in SSB bandwidth of this radio is 80dB at 2KHz (PM-noise=-114dBc/Hz), 97dB at 10Khz (PM-noise=-131dBc/Hz) and 111dB at 50KHz (PM-noise=-145dBc/Hz).


The next possible candidate is the pure "unspoiled" DDS. This option can be considered seriously for an HF down conversion LO, now that the spur levels have come down so much with the more recent 14 bit DDS chips by market leader Analog Devices. The following graph shows the AD9910 DDS at a 14.3MHz output frequency as measured by ADI. It should be 1dB worse in the 16MHz situation:

The original screen shot of the phase noise plot by ADI of the AD9910 can be found here. The AD9910 on the evaluation board is powered with very clean power supplies and clocked at 1GHz with a low phase noise Wenzel based clock signal. I have been able to reproduce the above PM-noise results! From 1KHz and outwards the AD9910 phase noise dives below the baseline needed in this frontend on the 40M band.

The output frequencies of the DDS needed with a down conversion frontend with a 9MHz IF are so far below the Nyquist limit, that spur levels are very low indeed. In relation with H-Mode mixer symmetry and the category 3 spurs, I have done quite a few spur measurements on the I0CG AD9951 DDS board clocked at 500MHz. The spurs with AD9951 cannot be neglected, but with AD9910, although it also has a 14 bit DAC, are considerably further down. In fact most of the many category 3 spurs I encountered with AD9951 disappear in the noise with AD9910.

Phase noise with DDS, when proper RF PCB layout guidelines are followed, depends mainly on the following 3 factors:

  • Reference clock phase noise.
  • Power supply noise.
  • Phase accumulator jitter.

Very important is the purity of the reference clock signal. When derived from an ultra low noise VHF crystal oscillator, the noise introduced by the reference clock can be so low that it does not add up to the end result except very close in!

The analog power rails need to be very clean, because power supply rejection ratio in the analog DDS circuits is not infinite! If noise levels on the power supplies are suppressed well enough they do not add up to the end result anymore.

Inevitable is the jitter of the DDS chip. The DDS acts as a very versatile digital divider with its phase accumulator. The jitter introduced by the phase accumulator is the only factor that cannot be improved and controlled from the outside. It is built in. The result is "residual" noise. The good news is that the residual noise is very minimal and has a slope of about 3dB per octave rather than the 6dB/octave or more experienced with analog oscillators. This means that close in phase noise can be very good with DDS, if the external factors are taken care of properly. Inevitably there is a point where the residual noise of the chip is overruled by the external noise of the clock and/or the power supplies. The following graph is taken from the datasheet and shows the residual phase noise performance of the AD9910:

Members of the latest family of 1GHz DDS chips like AD9910 and AD9912 are very attractive candidates for the frontends LO. Phase noise wise they seem to fit the bill. Reproducibility with off the shelf components seems possible. Spurs however always remain a problem as there are no good spurs..., but the levels are lower than ever. The choice has been made!

1GHz Reference Clock

AD9910 Prototype Board

AD9910 and SSB-Noise

AD9910 and PM-Noise

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